The Open Verification Methodology (OVM) and Universal Verification Methodology (UVM) are examples of standard transaction-based methodologies used to verify semiconductor chip designs. The OVM test bench environment typically includes, for example, the hardware or device under test (DUT) and the software or test bench including clocks, signals sent, and signals received. The methodologies are transaction-based, meaning that transactions between test bench components are constructs that represent different states of a signal. For example, a transaction representing a memory write command may include the address, verify, write, etc. A transaction may include higher level transactions as well as lower level transactions.
Transaction data for a simulation recorded in a fast signal database (FSDB) may be opened in a waveform view, and example of which is shown in FIG. 1. A waveform view allows an integrated circuit designer to visualize the signal transitions over time and the relationship of those signals with other signals in an integrated circuit design. In the OVM waveform view, transactions are typically shown as boxes with each box containing detailed information about a specific transaction for an individual component. For a particular component, the boxes containing transaction information are arranged in relative temporal order. While the waveform view provides a visualization of the relative temporal sequence of transactions for a particular component and between components of a DUT, the waveform view does not readily provide a sense of the absolute temporal sequence of transactions for the simulation.
Various other views of a simulation have also been developed to facilitate vent of integrated circuit design. For example, a temporal flow view (TFV) provides a sequential view of hardware components, state diagrams show the relationship between hardware components, and Unified Modeling Language (UML) diagrams may provide information about structure, behavior, and/or interactions of and/or between the system components.
For example, digital logic hardware events may be displayed in sequential temporal order using tools such as SpringSoft Novas Temporal Flow View (TFV). On the software side, tools such as Unified Modeling Language (UML) provide graphical representations of software systems. An example of a UML sequence diagram is shown in FIG. 2. In particular, the UML sequence diagram shows test bench components and the interactions between these components in their relative sequential temporal order. The primary use of UML has been to document a program or system. However, to facilitate system design verification it may be useful to generate and display interactions representing the dynamic behavior of a test bench simulation.